1. Field of Invention
The present invention relates to a method for manufacturing semiconductor devices. More particularly, the present invention relates to a method for manufacturing a dual gate oxide layer.
2. Description of Related Art
Integrated circuits are generally constructed from a combination of different devices and isolating structures. The devices are separated from each other through the isolating structures. The most commonly employed isolating structures include shallow trench isolation (STI). For example, the shallow trench isolation separates an input/output (I/O) device area from a core device area. After the formation of an isolation structure, a gate oxide layer is normally formed over the substrate surface. This gate oxide layer serves to facilitate the subsequent formation of a gate or connecting lines. Since a larger voltage is required for controlling the devices in an input/output area compared to a core device area, the input/output area must have a thicker gate oxide layer. Therefore, a thicker gate oxide layer must be formed in the input/output area to protect the devices against any adverse effects caused by a high operating voltage.
FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps in the formation of a dual oxide gate layer according a conventional method. First, as shown in FIG. 1A, a pad oxide layer 11 and a silicon nitride layer 12 are sequentially formed over a substrate 10. Then, photolithographic and etching processes are used to pattern the pad oxide layer 11 and the silicon nitride layer 12. Next, the substrate 10 is etched to form an opening 13 serving as a STI trench, wherein a liner oxide layer 14 can be formed on the bottom and sidewalls of the trench. Thereafter, using a chemical vapor deposition (CVD) method, an oxide layer is deposited into the trench. This is followed by a back etching operation using a chemical-mechanical polishing (CMP) method. Subsequently, the silicon nitride layer 12 is removed. Then, using hydrofluoric acid solution, the pad oxide layer 11 is also removed to form the block of oxide 15 as shown in FIG. 1B. Next, an oxide layer is formed over the substrate 10 and the surface of the oxide block 15 using a thermal oxidation process. A pattern of the input/output area is then defined on the oxide layer, and etched to form a first gate oxide layer 16. A second gate oxide layer 17 is then formed over the first gate oxide layer 16, the oxide block 15 and the substrate 10. Hence, a thicker gate oxide layer is formed above the I/O area, while a thinner gate oxide layer is formed over the core device area as shown in FIG. 1C. Finally, as shown in FIG. 1D, conventional techniques are used to form gates 18 on top of the I/O device and the core device.
In a conventional device manufacturing method, hydrofluoric acid is used to remove the pad oxide layer 11. Due to the isotropic etching of hydrofluoric acid in a wet etching process, recesses will form at the junction between the oxide block 15 and the gate surface 10. Recesses in the junction will lead to the occurrence of a kink effect. The kink effect caused by over-etching will lead not only to a lowering of the threshold voltage, but will also lead to an inferior quality for the subsequently deposited gate oxide layer and a lower device yield.
In light of the foregoing, there is a need in the art to provide a better method for manufacturing a dual gate oxide layer.